In collaboration with a research team at the University of Bremen, Verified Systems International GmbH has published a SysML model of the Ceiling Speed Control function specified for the ETCS onboard controller, the so-called European Vital Computer (EVC).
This model model is publicly available for practitioners and researchers who are interested in model-based testing. It is shown how different test strategies - all of them implemented in RTT-MBT - possess different test strength for uncovering specific errors that might be present in an EVC implementation. In particular, the capabilities of a novel equivalence class testing strategy that has recently been implemented in RTT-MBT are illustrated. A technical report decribing the underlying theory and its practical application is publicly available: A SysML Test Model and Test Suite for the ETCS Ceiling Speed Monitor. A summary of the results have been published as:
Cécile Braunstein, Anne Elisabeth Haxthausen, Wen-ling Huang, Felix Hübner, Jan Peleska, Uwe Schulze, Linh Vu Hong: Complete Model-Based Equivalence Class Testing for the ETCS Ceiling Speed Monitor. ICFEM 2014: 380-395
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