Verified Systems International GmbH

Quality Assurance for Embedded Systems

Test Engines

Cluster Architecture

The test system cluster architecture is based on dual CPU or 4-CPU PCs acting as cluster nodes. The nodes communicate and synchronise over a high-speed network (Myrinet or InfiniBand). A modification of the Linux operating system allows to run the test execution and evaluation algorithms in hard real-time on reserved CPUs, where scheduling is non-preemptive and controlled by the test system itself. The interrupts caused by interfaces to the system under test may be relayed to CPUs designated explicitly for their handling. This approach offers the opportunity to utilise high-performance standard hardware and the services provided by the widely accepted Linux operating system in combination with all mechanisms required for hard real-time computing. The cluster architecture presents an opportunity to distribute interfaces with high data throughput on different nodes, so that PCI bus overload can be avoided. In addition, the CPU load can be balanced by allocating test data generators, environment simulations and checkers for the behaviour of the system under test (“test oracles”) on dedicated CPUs.

Technical data

Supported Interfaces

AFDX, CAN, ARINC 429, Digital I/O, Analog I/O (incl. NTC, PTx), Analog Signal FFT, MIL-STD 1553, Ethernet, FireWire, Profibus, RS232, RS485, Parallel etc.


Scheduling accuracy: 3 microseconds
Cluster communication: Node-to-node communication latency < 50 microseconds, 10 GBit/s InfiniBand (copper) or 2GBit/s full duplex Myrinet (fiber)
I/O response time: Discrete output toggle 70 microseconds, Discrete input detection 85 microseconds, Analog output change 50 microseconds.

Specialised hardware

Made-to-measure fault-insertion units (line-resistance, inter-wire faults, short-circuits etc.)

Key features

Scalable Performance

RT-Tester test bench solutions offer several possibilities for scaling performance: CPU power needed for simulations and – if desired – on-the-fly checking of the system under test can be added by (1) switching from 2CPU to 4CPU cluster nodes or by (2) adding cluster nodes to the test bench. (3) Bottle necks on interface busses are resolved by distributing interfaces on different cluster nodes. The re-location of software and interfaces to other cluster nodes is easy to configure and does not require software changes, since RT-Tester communication software offers transparent access to all state data and events, regardless where a program resides within the cluster. High-speed cluster communication ensures data distribution with very low latency.

Modular Architecture

Our modular test bench architecture can integrate off-the-shelf components – e.g. PCs, standard interface boards – with customized HW/SW solutions – e.g. fault insertion units, special-purpose VME interfaces – easily assembled according to our customers’ needs.

Advanced Test Automation Techniques

Verified’s RT-Tester facilitates parallel hard real-time execution of multiple simulators and checkers. It supports various test specification languages which can be selected and combined according to the users’ preferences and skills.

Test Specification Tools Made-to-measure for Customers

RT-Tester offers domain-specific test language extensions – such as extensive AFDX simulation and evaluation libraries – and automatic test configuration support based on system under test configurations, as, for example, interface control document files. Graphical Test Management Interface for development, execution, evaluation, documentation of single test procedures as well as for complete test suites.