Test Case Generator TCGen

Verified's Test Case Generator TCGen is fully integrated into RT-Tester as an optional component, but it can also be integrated into other (customised or off-the-shelf) testing environments.

On unit test level, TCGen supports automated test case / test data generation for structural coverage testing:

• The expected functional behaviour of the unit under test is specified by means of pre- and postconditions.
• The test data needed to reach statement coverage (C0), branch coverage (C1) or modified condition/decision coverage (MC/DC) is created automatically, as far as this is possible. (Recall from theoretical computer science that the problem of automated test coverage generation is undecidable, so no algorithm able to create complete input data for full coverage of every program exists.)
• Unreachable code is detected and unreachability is proven, as far as possible.
• Future versions of TCGen will enable users to perform static analysis (e.g. automated array bounds checking) and property verification together with test case generation.

On SW, HW/SW and system integration level, TCGen performs automated test case and test data generation from models described in UML 2.0 or domain-specific formalisms.

Learn more about TCGen from the following publications available on the net:

With focus on unit testing:

Jan Peleska and Cornelia Zahlten: Integrated Automated Test Case Generation and Static Analysis. In Proceedings of the QA+Test 2007 International Conference on QA+Testing Embedded Systems, Bilbao (Spain) 17th - 19th October 2007. Best Paper Award.